发明名称 Scalable on chip network
摘要 A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.
申请公布号 US7051150(B2) 申请公布日期 2006.05.23
申请号 US20020207600 申请日期 2002.07.29
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 NAUMANN MARK W.;WALKER GARY A.;GARINGER NED D.;DORR MARTIN L.
分类号 G06F13/00;G06F13/36;G06F15/78 主分类号 G06F13/00
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