发明名称 |
Method of fabricating non-volatile memory cell adapted for integration of devices and for multiple read/write operations |
摘要 |
A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate and covers the electron trapping layer and the exposed bottom dielectric layer. A conductive layer is then formed on the top dielectric layer. The conductive layer, the top dielectric layer, the electron trapping layer and the bottom dielectric layer are patterned to form a stacked structure, wherein a width of the stacked structure is larger than a width of the trench. A source/drain region is formed in the substrate adjacent to the edges of the stacked structure. Because the electron trapping layer of the memory cell is divided into two isolation structures according to the invention, it is adapted for the integration of devices and for long-time operation.
|
申请公布号 |
US7049189(B2) |
申请公布日期 |
2006.05.23 |
申请号 |
US20040708904 |
申请日期 |
2004.03.31 |
申请人 |
POWERCHIP SEMICONDUCTOR CORP. |
发明人 |
CHANG KO-HSING;CHANG SU-YUAN |
分类号 |
H01L21/8238;H01L21/28;H01L21/336;H01L21/76;H01L21/8247;H01L29/792 |
主分类号 |
H01L21/8238 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|