发明名称 Decoder architecture system and method
摘要 A decoder may perform node data reordering for bit node processing and node data reordering for bit node to check node interconnections. The decoder may also utilize a single barrel shifting operation on data read from an edge memory for bit node processing or check node processing during a memory read operation. The decoder may also utilize a single format conversion on data read from an edge memory for bit node processing or check node processing. The decoder may also utilize a simplified check node process for check node processing.
申请公布号 US2006107181(A1) 申请公布日期 2006.05.18
申请号 US20050249197 申请日期 2005.10.13
申请人 DAVE SAMEEP;MO FAN 发明人 DAVE SAMEEP;MO FAN
分类号 H03M13/00 主分类号 H03M13/00
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