| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve a shift register having several cascaded stages (n-1, n, n+1). <P>SOLUTION: Each stage n consists of output of a node D and is connected to output at a stage n-1, output at a stage n+1, and first and second clock signals (ψ1, ψ2). The stages are constituted of a first semiconductor device (MN2) which is switched between high and low of the clock signal ψ1 and the first semiconductor device is controlled by potential of a node G. The node G is connected to output of the previous stage (n-1) via a second semiconductor device (MN1) to be controlled by the output at the stage n-1, connected to negative potential (V-) via a third semiconductor device (MN3) to be controlled by the output at the stage n+1 and connected to the second clock signal ψ2 via capacitance (C2). The shift register further has capacitance (C3) provided between the node G and the output at the stage n+1. The shift register is used for a driver for liquid crystal display. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
