发明名称 Automatic fault-testing of logic blocks using internal at-speed logic-BIST
摘要 System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple test vector, or can be performed by a field engineer on the actual board comprising the chip.
申请公布号 US2006107151(A1) 申请公布日期 2006.05.18
申请号 US20050141763 申请日期 2005.05.31
申请人 GENESIS MICROCHIP INC. 发明人 MUSHIRABAD VENKAT C.;SHETTIGARA RAJANATHA
分类号 G01R31/28 主分类号 G01R31/28
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