| 摘要 |
PROBLEM TO BE SOLVED: To ensure a backward compatibility with an existing system, to enable a timing to be detected with a high accuracy, to enable a residual carrier frequency error to be corrected with respect to an independent packet signal, and further to enable a clock error to be corrected. SOLUTION: This circuit is provided, at a front stage of a timing detecting means, with a second automatic frequency control means for detecting a carrier frequency error from a reception signal for correction. The circuit is provided with a steady phase rotation detecting and correcting means for detecting and correcting a steady phase rotation contained in a detection signal output from a signal detecting means. The circuit is provided with the steady phase rotation detecting and correcting means between a multi-carrier demodulating means and the signal detecting means. The circuit is also provided, between the signal detecting means and the steady phase rotation detecting and correcting means, with a phase rotation detecting and correcting means which inputs a carrier frequency error signal output from a first automatic frequency control means, and detects and corrects a phase rotation for each sub-carrier contained in a detection signal output from the signal detecting means. COPYRIGHT: (C)2006,JPO&NCIPI
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