LOW-POWER SERIALIZER WITH HALF-RATE CLOCKING AND METHOD

摘要

A serializer for multiplexing 2^N data streams, each data stream having a frequency of f/(2^N), N being a positive integer. The serializer comprises 2^N-1 instances of a dual-edge multiplexer flip-flop circuit, N frequency domains including a first frequency domain having the frequency f/2^N and a last frequency domain having a frequency f/2, and an output providing serialized data at frequency f clocked at half that rate. Thus, the highest clock signal frequency input into the serializer is f/2.