| 摘要 |
A configurable C-element logic cell and design method that can provide multiple variations of the C-element function from a one-off, custom cell implementation. Inputs of the C-element are tied off to supply voltages or other inputs. There are also provided circuits for logic reduction and completion detection having reduced circuit area and increased performance. The logic reduction circuits use wired logic in which a wired logic net has a load enabled from a high-impedance state. In a completion detection circuit, the enable signal of the load may be driven by the an exclusive OR of the completion outputs of both the an asynchronous module whose completion is being detected and an upstream module. |
