发明名称 Interleaver and de-interleaver systems
摘要 This invention relates to bit interleaver and de-interleaver apparatus, methods and processor control code for use in MIMO (Multiple-input multiple-output) communications systems, in particular MIMO systems employing OFDM (orthogonal frequency division multiplexing). We describe a block interleaver for a MIMO communications system, said interleaver being configured to interleave a block of N bits for spatially multiplexed transmission using a plurality of transmit antennas, said interleaver comprising: a matrix memory block configured to store an interleaving matrix, said matrix having a plurality of columns alpha and a plurality of rows sufficient to store said N bits: an input, coupled to said matrix memory block, to receive data to be interleaved; an output, coupled to said matrix memory block, to output interleaved data; and a controller, coupled to said matrix memory block, to control writing of said received data into said matrix row-by-row, and to control reading of said received data from said matrix column-by-column; and wherein the number of columns alpha is chosen such that said number of bits N is not an integral multiple of said number of columns alpha. This results in the last row of the matrix being incompletely filled. We also describe a corresponding de-interleaver and related interleaving and de-interleaving methods.
申请公布号 US2006107171(A1) 申请公布日期 2006.05.18
申请号 US20050254773 申请日期 2005.10.21
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SKRAPARLIS DIMITRIOS
分类号 H03M13/00;H04J99/00;H03M13/25;H04L1/00;H04L1/06;H04L27/26 主分类号 H03M13/00
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