发明名称 MEHRPROZESSORSYSTEM MIT BEOBACHTUNGSELEMENT
摘要 Multiprocessor system comprises memory elements (M), input output units (I/O) and a central bus system (CB). The input output unit accesses the memory elements using direct memory access over the bus system. A bus-monitoring unit (BS) monitors memory read-write access by input output units and the memory addresses generated. Based on said addresses interrupts are applied to individual processors.
申请公布号 DE50302815(D1) 申请公布日期 2006.05.18
申请号 DE2003502815 申请日期 2003.04.15
申请人 SIEMENS AG 发明人 TUPPA, WALTER
分类号 G06F13/32 主分类号 G06F13/32
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