| 摘要 |
<p>In a symmetrical phase-lock loop (PLL) device, first (I1P1, I1P2) and second (I2P1, I2P2) pairs of switches are disposed between (i) first and second outputs of a symmetrical time/voltage conversion block and (ii) first and second inputs of a voltage processing block. In addition, third (I3P1, I3P2) and fourth (I4P1, I4P2) pairs of switches are disposed upstream of the first and second inputs of the phase comparator (PC). Control means control the opening/closing of the first to fourth pairs of switches, such that: (a) during a first phase (P1), a first clock signal (Clkref) is connected to the first input of the comparator, a second clock signal (Clkdly) is connected to the second input of the comparator, the first output of the conversion block is connected to the second input of the processing block and the second output of the conversion block is connected to the first input of the processing block; and (b) during a second phase (P2), the first clock signal is connected to the second input of the comparator, the second clock signal is connected to the first input of the comparator, the first output of the conversion block is connected to the first input of the processing block and the second output of the conversion block is connected to the second input of the processing block, in order to compensate the static phase error.</p> |
