| 摘要 |
PROBLEM TO BE SOLVED: To reduce a penalty by a page error in time of DRAM memory access regardless of a data format to improve memory access speed of the whole system, in the system dealing with a plurality of data formats. SOLUTION: This system allowing memory access from a plurality of master devices has a memory controller, and the master devices each performing the regular and discrete memory access in each arbitrary access unit. The system has a means identifying the master device, and deciding the regular and discrete access, and has a means predicting the page error according to the access and previously performing page opening. COPYRIGHT: (C)2006,JPO&NCIPI
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