| 摘要 |
System has two assemblies transmitting frequencies (f1,f2). First signal is stabilized with phase lock loop, and third frequency (f3) formed. Second assembly signal is also phase locked, and produces signal equal to the first assembly frequency. Signal from second assembly is received by first assembly (7) and mixed with derivative signal (16). If the signal comparison produces a null, the signal received is confirmed, otherwise it is rejected. |
