发明名称 METHOD FOR MANUFACTURING ELECTRONIC DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To form a trench opening pattern with high precision by suppressing resist poisoning, when a dual-damascene interconnect lines are formed using Via first method. <P>SOLUTION: In the process for forming a dual damascene interconnect line, a concurrent capturing resin film 1 of cellulose is formed to fill a via hole 21 formed in an interlayer insulating film and to cover the surface of a cap layer 16. Preferably, it is partially carbonized in an inert atmosphere at a firing temperature of about 200°C. It is then irradiated with hydrogen plasma or hydrogen active species, containing hydrogen radicals and unnecessary concurrent capturing resin film 1a on the surface of the cap layer 16 is removed by etching thus forming a dummy plug 2. Suitably, the concurrent capturing resin film 1 is added with an acid agent, in advance. The dummy plug 2 captures or neutralizes basic substances, such as amines. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2006128543(A) 申请公布日期 2006.05.18
申请号 JP20040317719 申请日期 2004.11.01
申请人 NEC ELECTRONICS CORP 发明人 SODA EIICHI;YABE SACHIKO
分类号 H01L21/768;G03F7/20;H01L21/027;H01L21/3205;H01L23/52 主分类号 H01L21/768
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