发明名称 Mechanism for handling explicit writeback in a cache coherent multi-node architecture
摘要 A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
申请公布号 US2006106993(A1) 申请公布日期 2006.05.18
申请号 US20050321632 申请日期 2005.12.28
申请人 发明人 KHARE MANOJ;LOOI LILY P.;KUMAR AKHILESH
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
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