发明名称 Method and apparatus for stacking electrical components using via to provide interconnection
摘要 An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.
申请公布号 US2006102993(A1) 申请公布日期 2006.05.18
申请号 US20040987468 申请日期 2004.11.12
申请人 发明人 TSAI CHEN J.;LIN CHIH W.
分类号 H01L23/02 主分类号 H01L23/02
代理机构 代理人
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