| 摘要 |
<p>The present communications channel synchronous micro-cell system for integrating circuit and packet data transmissions functions to blend both circuit and packet technology together to carry both constant bit rate and variable bit rate traffic with no added packet or jitter delay for constant bit rate traffic and no added circuit setup delay for variable bit rate traffic. This is accomplished by the use of a micro-cell structure for all information that is transmitted over a communication channel. The data stream comprises a series of frames, each of which consists of a predetermined number of micro-cells. The micro-cells are fixed in size, with a header, like Asynchronous Transfer Mode, but their similarity stops there. The header is a flag which indicates the type of payload that is placed in the micro-cell associated with that header. When the header indicates a payload that is synchronous with the communication medium, that micro-cell is being used as a time slot in a circuit switched sense. When the header indicates a payload that is asynchronous with the communication medium, that micro-cell is being used to transfer packets of data, which are routed by the address data embedded in the header of the packet data, independent of the micro-cell location in the frame. <IMAGE></p> |
