| 摘要 |
A scheme is described for distributing data operations on an irregular data stream over multiple stages (404, 406, 704, 706) of a data aligner (400, 700) to generate a regular data stream having continuous filled byte positions. In one particular embodiment, the number of unaligned data scenarios may be reduced through the use of data stream element mapping. A complex data stream may be mapped (835) onto a simple data stream with only the addition of multiplexers (460, 470, 760, 770, 775) and simple logic to the data aligner. The implementation in network protocol related hardware, where a data stream is encoded and decoded for error detection and correction, may lead to a faster and more efficient pipelined design of checkers and generators, thereby, making them more desirable for higher frequency and higher bandwidth designs. |
