发明名称 TRANSISTOR WELL BIAS SCHEME
摘要 <p>A method of reducing the operating voltage level of a MOS transistor formed in a well, comprising drawing a current from the well and thereby forward biasing the well, while the well potential is allowed to vary according to inherent transistor characteristics.</p>
申请公布号 KR20060045784(A) 申请公布日期 2006.05.17
申请号 KR20050031610 申请日期 2005.04.15
申请人 ZARLINK SEMICONDUCTOR AB 发明人 LEREVEREND REMI
分类号 H01L27/04;H01L29/78;H01L21/822;H01L21/8234;H01L27/088;H01L29/76;H03F3/16;H03F3/45;H03K17/00;H03K17/041;H03K19/094 主分类号 H01L27/04
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