发明名称 |
Analyzing instruction completion delays in a processor |
摘要 |
A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group. |
申请公布号 |
US7047398(B2) |
申请公布日期 |
2006.05.16 |
申请号 |
US20020210358 |
申请日期 |
2002.07.31 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KURIHARA TOSHIHIKO;LE HUNG QUI;MERICAS ALEXANDER ERIK;MIRABELLA ROBERT DOMINICK;OKUNO MICHITAKA;TOKORO MASAHIRO |
分类号 |
G06F11/34;G06F9/38 |
主分类号 |
G06F11/34 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|