发明名称 |
Method for producing test patterns for testing an integrated circuit |
摘要 |
A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.
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申请公布号 |
US7047174(B2) |
申请公布日期 |
2006.05.16 |
申请号 |
US20010847487 |
申请日期 |
2001.05.02 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
KOH ALEX S. Y.;CARLIN ALAN JOSEPH;TUMIN KENNETH PAUL;CARSON, JR. HUBERT GLENN |
分类号 |
G06F9/455;G01R31/3183 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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