Bi-mode sense amplifier with dual utilization of the reference cells and dual precharge scheme for improving data retention

摘要

An electronic memory system includes a memory array of a number of pair of bitlines comprising a true bitline and a complementary bitline. A first normal cell connects to the true bitline (BT 0 ) and a second normal cell connects to the complementary bitline (BC 0 ). A first reference cell connects to the true bitline and a second reference cell connects to the complementary bitline. A clock generates timing pulses including short circuiting-equalization pulses and selectively provides reference potential pulses in a reference potential mode of operation. A sense amplifier has a true terminal connected to the true bitline and a complementary terminal connected to the complementary bitline. An equalization short circuiting circuit connects to the clock and to the true bitline and the complementary bitline for short circuiting the true bitline and the complementary bitline together in response to the short circuiting pulses to equalize the electric potential thereon as a function of short circuiting-equalization. A precharge circuit connects at least one of the true bitline and the complementary bitline to an electrical potential selected from a higher voltage or low voltage reference potential in response to a precharge equalization clock pulse from the clock generator.