| 摘要 |
A phase matched clock divider includes a first feed-through flip-flop that receives a first input clock signal, and in response, provides a first output clock signal having the same frequency. The first feed-through flip-flop is enabled and disabled in response to a first reset signal. A plurality of series-connected flip-flops each receives the first input clock signal, and in response, provides a divided output clock signal. Each of the series-connected flip-flops is enabled and disabled in response to a second reset signal. The first and second release signals asynchronously disable the associated flip-flops in response to a third reset signal. The first release signal synchronously enables the first feed-through flip-flop in response to the third reset signal and a release clock signal. The second release signal enables the series-connected flip-flops in response to the third reset signal and a release control signal.
|
