发明名称 |
Apparatus and method for address selection |
摘要 |
An apparatus for address selection including a first storage element and a second storage element coupled to an input bus. The first storage element stores a first address segment and the second storage element stores a second address segment upon the receipt of respective complementary clock signals. An internal address bus propagates the address segments together.
|
申请公布号 |
US7046580(B1) |
申请公布日期 |
2006.05.16 |
申请号 |
US20040877909 |
申请日期 |
2004.06.25 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
MANAPAT RAJESH;SRINIVASAGAM KANNAN;MASTIPURAM RITESH |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|