| 摘要 |
Within a processor (2) providing single instruction multiple data (SIMD) type operation, single data processing instructions can serve to control processing logic (4, 6, 8, 10) to perform SIMD-type processing operations upon multiple independent input values to generate multiple independent result values having a greater data width than the corresponding input values. A repartitioner in the form of appropriately controlled multiplexers serves to partition these result data values into high order bit portions and low order bit portions that are stored into separate registers (38, 40). The required SIMD width preserved result values can be read from the desired high order (38) result register or low order result register (40) without further processing being required. Furthermore, the preservation of the full result facilitates improvements in accuracy, such as over extended accumulate operations and the like. |
