发明名称 |
Two-stage block-synchronization and scrambling |
摘要 |
A two-stage block synchronization and scrambling module includes a synchronization PRNG module, a scramble PRNG module, a summing module, and a storage module. The synchronization PRNG module is clocked once per N+1 bit PCS frame (N arbitrary) to produce a synchronization bit and a pseudo-random starting state for the scramble PRNG. The scramble PRNG module is clocked N times per PCS frame to produce a cipher stream starting with a pseudo-random state from the synchronization PRNG. The summing module is operably coupled to sum the cipher stream and a PCS frame payload to produce scrambled payload. The storage module is operably coupled to store the scrambled payload with the synchronization bit. Synchronization bits from successive frames are a running bit-serial representation of the synchronization PRNG state and are used by the receiver to synchronize with the transmit scrambler.
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申请公布号 |
EP1655917(A2) |
申请公布日期 |
2006.05.10 |
申请号 |
EP20050023322 |
申请日期 |
2005.10.25 |
申请人 |
BROADCOM CORPORATION |
发明人 |
POWELL, RICHARD SCOTT;SHEN, BA-ZHONG;UNGERBOECK, GOTTFRIED, DR. |
分类号 |
H04L25/03 |
主分类号 |
H04L25/03 |
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