| 摘要 |
A "return-to-zero" (RZ) current switching DAC includes an analog output node for which a "zero" potential has been defined. The outputs of a plurality of current sources are selectively directed to respective intermediate nodes in response to respective control signals, which are varied in synchronization with a clock signal CK. A plurality of RZ circuits are connected between respective intermediate nodes and the analog output node. In a preferred embodiment, each RZ circuit directs the current applied to a respective intermediate node to ground or to the analog output node in synchronization with CK. An output network pulls the analog output node to the "zero" potential when currents applied to the intermediate nodes are directed to ground.
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