发明名称 Ternary CAM bitcells
摘要 Two new ternary CAM bitcell design options are presented that provide compact layout solutions while maximizing matchline channels routing through the cells. In both layouts, the first inventive layout, an asymmetric layout of the 6T-SRAM bitcell is used to improve ease of layout, density, and performance of ternary CAM cells. In the second inventive layout, n-type diffusions for the SRAM bitcell and the comparison circuit are separated, creating a bitcell having a more even cell aspect ratio.
申请公布号 US7042747(B1) 申请公布日期 2006.05.09
申请号 US20050041094 申请日期 2005.01.19
申请人 LSI LOGIC CORPORATION 发明人 CASTAGNETTI RUGGERO;VENKATRAMAN RAMNATH;GLENN JOSEPH E.
分类号 G11C15/00 主分类号 G11C15/00
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