High voltage tolerant ESD design for analog and RF applications in deep submicron CMOS technologies

摘要

The invention describes structures and a process for providing ESD semiconductor protection with reduced input capacitance that has special advantages for high frequency analog pin I/O applications. The structures consist of a first and second NMOS serial pair whose capacitance is shielded from the I/O pins by a serial diode. The first serial pair provides an ESD voltage clamp between the I/O pin and the Vcc voltage source. The second pair provides an ESD voltage clamp between the I/O pin and Vss, or ground voltage source. A NMOS device whose gate is dynamically coupled to the ESD energy through capacitance and a RC network enhances the triggering of both pairs. The serial pairs can be used separately to match specific application requirements or used together.