| 摘要 |
First to third logic circuits and first to third static random access memories (SRAMs) are formed on one chip. Power to the first and third logic circuits and their SRAMs is shut off as required, while power to the second logic circuit and its SRAM is kept supplied. The third SRAM has the largest memory capacity. The average channel width of the first to third SRAM cell arrays is set at a half or less of that of the other circuit blocks, and the channel impurity concentration of the second and third SRAM cell arrays, which operate at low speed, is set higher than that of the first SRAM cell array, which operates at high speed, by additional ion implantation. By these settings, MOS transistors of low threshold voltage (Vt) are provided for the first SRAM cell array, while MOS transistors of high Vt are provided for the second and third SRAM cell arrays for leakage reduction.
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