| 摘要 |
A multiply accumulate unit ("MAC") that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8x8 operations, four 16x16 operations, or one 32x32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8x8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.
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