发明名称 Structure for reducing stress-induced voiding in an interconnect of integrated circuits
摘要 A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.
申请公布号 US7042097(B2) 申请公布日期 2006.05.09
申请号 US20030455849 申请日期 2003.06.06
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 YAO CHIH-HSIANG;HSIA CHIN-CHIU;WAN WEN-KAI
分类号 H01L23/48;H01L21/768;H01L23/52;H01L23/528;H01L29/40 主分类号 H01L23/48
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