Gated clock circuit with a substantially increased control signal delay

摘要

A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to, and in phase with, the pulse width of a master clock signal, while at the same time substantially increasing the maximum value of the delay.