| 摘要 |
Provided is a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus line by using the delay of an internal data strobe signal's falling for a certain amount of time as an input data strobe bar signal. Moreover, by using a skew detection circuit, it is possible to detect a skew tDQSS between a clock and a data strobe, and the skew tDQSS is automatically compensated by the skew compensation circuit. From the perspective of a timing error between the clock and the data strobe, therefore, the write operation of the DDR SDRAM has twice the timing margin (0.5tCK) compared to that of the related art. This means that a stable, high-speed write operation of the DDR SDRAM can be made possible.
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