| 摘要 |
<p>A semiconductor memory system has command/address data (CA) transmitted from the memory controller to the semiconductor memory, and memory data (DQ) transmitted between the memory controller and the semiconductor memory. A clock signal (CLK) can be transmitted between the memory controller and the semiconductor memory, and the zone identifying the clock signal (CLK) has 'unmasked' clock signal flanks. The write/read command (WRITE) from the memory data (DQ) is supported with a 'time-delayed' identifying zone (3) in the clock signal (CLK) and transmission of a first bit of the memory data (DQ) of a burst can be signaled with the clock signal flank following the identifying zone (3). An independent claim is included for a method for data transmission.</p> |
