| 摘要 |
A processor with cache way prediction and method thereof. The processor includes a cache way prediction unit for predicting at least one cache way for selection from a plurality of cache ways. The processor may further include an instruction cache for accessing the selected at least one cache way, where the selected at least one cache way is less than all of the plurality of cache ways. The method includes predicting less than all of a plurality of cache ways for selection and accessing the selected less than all of the plurality of cache ways. In both the process and method thereof, by accessing less than all of the plurality of cache ways, a power consumption and delay may be reduced.
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