发明名称 Methods of forming planarized multilevel metallization in an integrated circuit
摘要 A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.
申请公布号 US2006094232(A1) 申请公布日期 2006.05.04
申请号 US20040976539 申请日期 2004.10.29
申请人 SU CHIN-TA;LAI JERRY;YEN YU-LIN 发明人 SU CHIN-TA;LAI JERRY;YEN YU-LIN
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 代理人
主权项
地址