发明名称 Serial data link using decision feedback equalization
摘要 A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.
申请公布号 US2006093028(A1) 申请公布日期 2006.05.04
申请号 US20040978755 申请日期 2004.11.01
申请人 LSI LOGIC CORPORATION 发明人 BALAN VISHNU;CAROSELLI JOSEPH P.JR.;LIU YE;DESAI CHINTAN M.;CHERN JENN-GANG
分类号 H03H7/30 主分类号 H03H7/30
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