| 摘要 |
A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.
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