Access of two synchronous busses with asynchronous clocks to a synchronous single port ram,申请号EP20030447153-传众专利搜索

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发明名称	Access of two synchronous busses with asynchronous clocks to a synchronous single port ram
摘要
申请公布号	EP1489521(B1)	申请公布日期	2006.05.03
申请号	EP20030447153	申请日期	2003.06.16
申请人	STMICROELECTRONICS BELGIUM N.V.	发明人	LEVY, DAVID
分类号	G06F13/16;G11C7/10	主分类号	G06F13/16
代理机构		代理人
主权项
地址

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