发明名称 |
Parallel cache interleave accesses with address-sliced directories |
摘要 |
A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split according to the interleaved cache and interleaving of the cache directory is independent of address bits used for cache interleaving.
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申请公布号 |
US7039762(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20030436217 |
申请日期 |
2003.05.12 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
NAVARRO JENNIFER A.;SHUM CHUNG-LUNG K.;TSAI AARON |
分类号 |
G06F12/00;G06F12/08;G06F12/10 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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