发明名称 |
Circuit for controlling the clock supplied to a state controller in a data transfer control device according to states of first and second devices |
摘要 |
In a clock generating circuit, clocks generated therein are distributed by a clock distribution control circuit for every circuit block. In a clock output control circuit, a clock command is decoded by a clock command decoder and output of the clocks is controlled for every circuit block. A data transfer control device having a clock control circuit functions as a first device or a second device to transfer data as a host or a peripheral. When the data transfer control device function as a second device and in an idle state, it controls clock output to a state controller which controls switching between a host function and a peripheral function.
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申请公布号 |
US7039826(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20030379686 |
申请日期 |
2003.03.06 |
申请人 |
SEIKO EPSON CORPORATION |
发明人 |
SAITO NOBUYUKI;SHIMONO HIROAKI |
分类号 |
G06F1/04;G06F13/38;G06F1/06;G06F1/32;G06F13/42 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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