Dynamic memory word line driver scheme

摘要

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V_ss and V_dd, and for providing a select signal at levels V_ss and V_dd, a high voltage supply source V_pp which is higher in voltage than V_dd, a circuit for translating the select signals at levels V_ss and V_dd to levels V_ss and V_pp and for applying it directly to the word lines whereby an above V_dd voltage level word line is achieved without the use of double boot-strap circuits.