发明名称 |
Control loop apparatus and method therefor |
摘要 |
In the field of optical communications, the need to remove jitter from a Synchronous Digital Hierarchy (SDH) or Synchronous Optical NETwork (SONET) datastream is recognized. Consequently, the present invention provides a First-In-First-Out (FIFO) buffer having a read-out clock frequency that is controlled in response to a depth error of the FIFO buffer. The control of the read-out clock frequency is achieved by a hardware control loop coupled to the FIFO buffer. The period of the control loop is a product of the frequency at which the depth error of the FIFO buffer is acquired and another factor. The another factor is the number of states of logic employed by the control loop raised to an integer power.
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申请公布号 |
US7039145(B2) |
申请公布日期 |
2006.05.02 |
申请号 |
US20030375229 |
申请日期 |
2003.02.27 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
OLD GORDON |
分类号 |
H04L25/00;H04J3/06;H04L7/00;H04L25/40 |
主分类号 |
H04L25/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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