| 摘要 |
A multi-mode Reed-Solomon decoder is disclosed. According to the invention, by simplifying the Peterson-Gorenstein-Zierler (PGZ) algorithm the goal of correcting different numbers of errors (t<=3) using a single hardware architecture is achieved. Through optimization without requiring finite field inversion operations, the hardware and the computing efficiency are both improved. The invention also discloses a register transistor level (RTL) hardware architecture to applied in error control codes (ECC) between a processor and a memory and other high-speed communication systems.
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