发明名称 Pipeline Operation Method of Video Management Apparatus and Bit Rate Control Method
摘要 Disclosed is a pipeline-type operation method which can reduce idle operations of hardware modules. The pipeline-type operation method for a video processing apparatus including a plurality of hardware modules includes the steps of constructing a plurality of hardware modules according to functions required to process video; arranging the hardware modules according to a sequence of input data flow, and inputting a first predetermined unit of data into a first hardware module from among the arranged hardware modules; transferring processed data from the first hardware module to a second hardware module when the predetermined unit of data inputted into the first hardware module has been processed, and receiving a next predetermined unit of data; repeating the transferring and receiving steps, in which each input data are processed by the hardware modules according to a sequence of the hardware modules, until all of the hardware modules are operated; ions receiving and processing data processed in a previous step by the previous hardware module in a sequence of data flow by each of the hardware modules; and repeating the receiving and processing steps until no predetermined unit data to be inputted remains.
申请公布号 KR100575962(B1) 申请公布日期 2006.05.02
申请号 KR20030101714 申请日期 2003.12.31
申请人 发明人
分类号 H04B1/40;H04N7/12;H04N7/26;H04N7/50 主分类号 H04B1/40
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