SELF-CONFIGURING INTERFACE ARCHITECTURE ON FLASH MEMORIES

摘要

A LOW-POWER INTERFACE FOR NONVOLATILE WRITEABLE MEMORY (110) IS DESCRIBED. THE INTERFACE INCLUDES AN INPUT BUFFER (220) AND AN OUTPUT BUFFER (224). THE INPUT BUFFER RECEIVES INPUT SIGNALS HAVING ONE OF A NUMBER OF PAIRS OF LOGIC LEVELS. THE INPUT BUFFER (220) IS COUPLED TO THE NONVOLATILE WRITEABLE MEMORY (110) AND COUPLED TO THE SAME POWER SUPPLY AS THE NONVOLATILE WRITEABLE MEMORY. THE INPUT BUFFER (220) TRANSLATES THE INPUT SIGNALS RECEIVED TO THE SIGNAL LEVEL USED BY THE NONVOLATILE WRITEABLE MEMORY (110). THE OUTPUT BUFFER (224) IS COUPLED TO THE NONVOLATILE WRITEABLE MEMORY (110) AND IS COUPLED TO A DIFFERENT POWER SUPPLY FROM THE INPUT BUFFER (220) AND THE NONVOLATILE WRITEABLE MEMORY (11 0). THE OUTPUT BUFFER (224) TRANSLATES THE SIGNALS RECEIVED FROM THE NONVOLATILE WRITEABLE MEMORY (110) TO THE SAME SIGNAL LEVELS AS THE INPUT SIGNAL (220). THE INPUT BUFFER (220) AND OUTPUT BUFFER (224) UTILIZE INPUT/OUTPUT SIGNALS HAVING LOGIC LEVELS COMPATIBLE WITH COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) TECHNOLOGY.