发明名称 METHOD AND APPARATUS FOR DEFERRED DECISION SIGNAL QUALITY ANALYSIS
摘要 <P>PROBLEM TO BE SOLVED: To provide a signal analysis circuit including a sampling circuit. <P>SOLUTION: The sampling circuit is operative to sample the characteristics of an input signal at various points within a bit window in response to a sample clock signal. A sampling control circuit is coupled to the sampling circuit and is operative to provide the sample clock signal in response to a sample control signal. The sample clock signal provides a variable time function such that the input signal characteristics may be sampled at several times during the input signal or bit window period. A control circuit is coupled to the sampling circuit and the sampling control circuit, and is operative to provide the sample control signal in response to the number of times the input signal exhibits a signal characteristic of interest. In an exemplary embodiment, the characteristic of interest is a reference pattern that may be synchronized with the input data signal. The reference pattern is provided by a pattern generation circuit that is resident within a larger comparison and counting circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006115488(A) 申请公布日期 2006.04.27
申请号 JP20050276364 申请日期 2005.09.22
申请人 SYNTHESYS RESEARCH INC 发明人 WASCHURA THOMAS E;WILLIS ANDREI;FINCHER CLINT
分类号 H04L7/02;H04L25/02;H04L25/08 主分类号 H04L7/02
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