| 摘要 |
PROBLEM TO BE SOLVED: To provide a multi purpose analog front end and a timing generator (AFE/TG) integrated circuit capable of supplying a horizontal timing signal and a vertical timing signal to many kinds of distinct image sensors. SOLUTION: Each of AFE/TGs 104 to 106 has an output mode for outputting binarized sensor data to a single digital image processor (DIP) 107 without making a plurality of the same AFE/TGs interpolate a multiplexing circuit. Each of the AFE/TGs 104 to 106 comprises a processor for performing a program. Detailed timing of the horizontal timing signal and the vertical timing signal to be outputted from the AFE/TGs 104 to 106 is to be controlled by performing this program. The program is to be loaded to the AFE/TGs 104 to 106 via a serial bus at a time of boot. The processor is to be supplied a clock from a clock signal having comparatively long clock period. The processor can generate and control a substantially larger timing signal in resolution than a processor clock period by a DLL and a related set/reset circuit. COPYRIGHT: (C)2006,JPO&NCIPI
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