发明名称 Chip-size package manufacture involves patterning dielectric layer to form openings exposing conductive lines
摘要 <p>Dielectric layer (104) is patterned on a contact conductive layer, to form openings exposing a portion of a conductive line (103) of a dice (101). The conductive material of thickness 12-18 mu m is filled into the openings and is patterned. A UV curing type material layer is patterned to form openings exposing the conductive material, and solder balls are welded to the openings. An independent claim is also included for: the chip-size package structure.</p>
申请公布号 DE102004058413(A1) 申请公布日期 2006.04.27
申请号 DE20041058413 申请日期 2004.12.03
申请人 ADVANCED CHIP ENGINEERING TECHNOLOGY INC., HSINCHU 发明人 YANG, WEN KUN
分类号 H01L21/50;H01L21/66;H01L21/78;H01L23/28 主分类号 H01L21/50
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